1. Field of Invention
The present invention relates generally to RF circuits and more particularly to switches usable for activating and deactivating RF paths, including switching an antenna between multiple transit paths, and other applications.
2. Related Art
FIG. 1 illustrates a prior art RF circuit 100 coupled to an antenna 110. The circuit 100 comprises a number of transit paths 120 and an antenna switch 130 that couples the antenna 110 to the several transit paths 120. Each transit path 120 includes a power amplifier 140 and a receiver amplifier 150 alternately joined to the antenna switch 130 by a switch 160. Within the antenna switch 130, each transit path 120 is switchably coupled to the antenna 110 by a series switch 170 and optionally also switchably coupled to ground by a parallel switch 180.
As shown in FIG. 1, when one transit path 120 is coupled to the antenna 110 (said to be in the ON mode), the series switch 170 for that transit path 120 is closed while the parallel switch 180 is open, whereas the switches 170, 180 are reversed for all other transit paths 120 (OFF mode). While the antenna switch 130 will work with only the serial switches 170, the addition of the parallel switches 180 provides greater isolation by grounding the transit paths 120 that are not in use.
Switches 170, 180 are commonly implemented with a number of transistors arranged in series, as illustrated by the prior art switches 200, 300 of FIGS. 2 and 3, described in more detail below, where the transistors are controlled together to alternately open and close. Series transistors are sometimes referred to as a stack. The gates of the transistors in the stack are controlled by a high-resistance bias network. A series switch 170, when in the ON mode, is floating and has almost a 0V voltage drop across it, the transistors behaving as resistors in series. When the series switch 170 is in the OFF mode, each transistor behaves effectively as a capacitor with the input side of the series of transistors is grounded through the parallel switch 180 while the output side of the series of transistors sees the entire RF voltage swing, since the output side of every series switch 170 is connected to a common node 190 before the antenna 110. If the voltage at the common node 190 is the RF voltage (VRF), and if the series switch 170 includes N transistors, then VRF/N must be kept below the breakdown voltage of the transistors.
The overall capacitance of a transistor between source and drain, when off, is the contribution of the source to gate, drain to gate, source to channel, and drain to channel capacitances. The product of the resistance in the ON mode (Ron) and the capacitance in the OFF mode (Coff) of the stack in this RF domain yields a Figure of Merit (Ron*Coff) which represents the RF performance of the switch. Another metric of the transistors in a switch 170, 180 is their gate capacitance, the capacitance of the gates to the bias network in the DC domain used to control the transistors. The switching speed to open or close a switch 170, 180 is proportional to the time constant, the product of the gate capacitance and the resistance of the bias network.
FIGS. 2 and 3 provide two examples of prior art switches 200, 300 commonly implemented in CMOS. Both switches 200, 300 include multiple transistors in series, and are suitable for use as either serial or parallel switches 170, 180. In a first example, shown in FIG. 2, the switch 200 includes multiple transistors 210 arranged in series, source to drain. A resistor 220 is associated with each of the multiple transistors 210, the resistor 220 for a given transistor 210 being connected in parallel between the source and the drain of that transistor 210. The gates of the multiple transistors 210 are controlled together by a bias network comprising a common control line 230 and a number of resistors 240, where each transistor 210 is connected to the common control line 230 by one of the resistors 240. In the configuration of FIG. 2, the switching time is a function of the product of the gate capacitance and the resistance of the bias network. All transistors 210 are controlled together, so the switching time is optimum.
FIG. 2 also shows an equivalent circuit 250 to represent the switch 200 in the OFF mode to illustrate the power loss through the bias network. It is noted that the resistors 220 in the switch 200 are omitted from the equivalent circuit 250, for simplicity. In circuit 250, each transistor 210 is represented by two capacitors, one for the capacitance on the source side of the gate and the other for the capacitance on the drain side of the gate. Since the entire RF voltage (VRF) is distributed across the stack of 6 transistors 210, each capacitor 255 in the equivalent circuit 250 sees 1/12 of the VRF, as shown. Power, in electrical circuits, is proportional to the square of the voltage and inversely proportional to the resistance (V2/2R). As illustrated, at one end of the stack a resistor 240 sees all of the VRF less the (1/12)VRF dissipated across one half of the associated transistor 210, hence it sees (11/12)VRF. The voltage seen be each successive resistor 240 in the stack is lower by (1/6)VRF until the last resistor 240, which sees only (1/12)VRF. The power loss due to each resistor 240 of the bias network therefore depends on its position relative to the stack.
In the example of FIG. 2, where there are 6 transistors 210 in series, the power loss for each resistor 240 is summed to arrive at the overall loss. In this example, the denominator (2R) is the same for each term, and the numerator is the sum of the squares of the voltages which is (112/122+92/122+72/122+52/122+32/122+1/122)VRF2. This can be generalized for N resistors to ((2N−1)2+ . . . +52+32+1))VRF2/(2N)2. With increasing numbers of transistors 210 the sum of the squares ((2N−1)2+ . . . ) dominates over the squared term (2N)2, thus, the overall power loss increases for each additional transistor 210 in the stack.
In a second example, shown in FIG. 3, a switch 300 also includes multiple transistors 210 arranged in series, source to drain. Similarly, a resistor 220 is associated with each of the multiple transistors 210, with the resistor 220 for a given transistor 210 is connected in parallel between the source and drain of that transistor 210. The bias network in this example also comprises one resistor 240 for each transistor 210, however, in this configuration the resistors 240 are connected in series along the control line 230. The first resistor 240 is disposed between the first gate and the DC control (not shown), the second resistor 240 is disposed between the first and second gates, and so forth, as illustrated.
The example of FIG. 3 is optimized to minimize power loss as the voltage drop across each resistor 240 is about the same, VRF/6, except for the first one in the series which sees a voltage drop of only VRF/12, as shown in the equivalent circuit 350 in FIG. 3. Therefore, the power loss becomes a constant and does not depend on the number of transistors 210 in series as the number of transistors 210 in the stack is increased. While power loss is minimized, switching time suffers in the example of FIG. 3 because the transistors 210 open progressively from one end of the stack to the other.
Another parameter of switches 200, 300 that depends on the number of transistors 210 in the stack is the linearity of the switch 200, 300. For some switches 200, 300, the linearity requirement can be very high, such as for antenna switches 130 since the antenna switch 130 is typically the last component prior to the antenna 110. Without filtering between the antenna switch 130 and the antenna 110, spurious and/or harmonic signals at the antenna 110 can interfere with the intended signal. As an example, the second harmonic of band 17 can fall into the GPS receive band and therefore about 110 dBc of harmonic rejection is required.
The number of transistors 210 in a stack of a switch 170, 180 of an antenna switch 130 is generally dictated by the minimum number of transistors 210 necessary to handle the required power and the minimum number necessary to provide the desired linearity of the switch 170, 180, whichever is larger. Given a required number of transistors, switching time and power loss are then balanced using the resistance of the bias network as the variable. In the case of switching time, decreasing resistance decreases the switching time proportionally. However, power loss scales as the inverse of the resistance, so decreasing resistance increases the power losses of the bias network.